Word-Oriented Memory Test and Coupling Fault Coverage: a RAW and RAW1 Case Study

Post-Silicon validation is considered a valued process that ensures that the integrated circuit has been manufactured correctly. Testing memories, specifically, is thought challenging due to the high-density nature of memory circuits, which can lead to faults coupled to adjacent cells. Research in this field is still ongoing, offering several different test algorithms. In this paper, two Built-In Self-Test circuits of RAW and RAW1 algorithms, respectively, are designed, verified, and compared, demonstrating the need and benefit to convert typical bit-oriented MARCH tests for word-oriented memories. RAW1 is shown to have 100% coupled cell fault coverage, while still requiring half the clock cycles that RAW requires to run a full test on the same memory.

I. Introduction

Among the different algorithms that have appeared for memory testing, MARCH is rather the most encountered category of algorithms [1]. There have been many different MARCH algorithms proposed over the years [2], [3], [4], [5], [6]. The primary objective in memory post-silicon testing is to determine an algorithm that detects all possible memory faults in as few clock cycles as possible. S. Hamdioui et al. propose March RAW algorithm, targeting all static and a variety of dynamic faults and March RAW1 as a shortened version of the first that aims only static faults [7].