SOT-MRAM-Based LUT Cell Design for Area- and Energy-Efficient FPGA

Although SOT-MRAM based non-volatile lookup tables (LUTs) can be efficiently employed to reduce the area of field programmable gate array (FPGA), the selector containing the multiplexer (MUX) tree for accessing the LUT cells still takes a dominant portion of LUT area. In this brief, we present a novel area-efficient SOT-MRAM-based LUT that can efficiently remove the last stage selector. In the proposed LUT, the role of the last stage selector, which is selecting a cell among the preceding two cells, has been implemented using SOT-MRAM cell with additional vertical metal lines within the LUT cell. The control of the metal lines requires only a small number of switches and controller, incurring minor hardware resources compared to the last stage selector MUX tree. As a result, almost half of the entire MUXs in the selector can be eliminated and significant area reduction can be achieved. In addition, the proposed LUT cell also offers an improvement in read energy and speed by reducing the BL capacitances of the metal lines involved in the read operations. The post-layout simulation results using 28nm CMOS process show that the proposed SOT-MRAM LUT design achieves 34.1% of area and 20.1% read energy reduction with 22.1% read speed improvement when compared to conventional SOT-MRAM based LUT.

I. Introduction

In field programmable gate array (FPGA), a significant amount of lookup-tables (LUTs) are used to implement complex logic gates in the configurable logic blocks (CLBs), and the LUTs take up a large portion of the entire FPGA area [1], [2]. The conventional CMOS-based LUT uses static random access memory (SRAM) cells to store the truth table data of the designated logic, which suffers from a large area and leakage power. Recently, the use of spin-orbit torque magnetic random access memory (SOT-MRAM) based non-volatile lookup tables (LUT) has been studied for implementing CLBs due to their high cell area efficiency and nonvolatility compared to SRAM [3], [4], [5]. Although SOT-MRAM based LUTs offer several advantages, the selector MUX tree used for accessing LUT cells still takes up a large portion of the overall LUT area [3], [5]. So, the potential for reducing the overall LUT area through the use of SOT-MRAM is still limited.