High Speed SerDes Design on Flip Chip Package Substrate

High speed SerDes design are becoming so fast that signal integrity problems become more prominent. Whether using the non-return to zero (NRZ), or working the 4-level pulse amplitude modulation (PAM-4), substrate design challenges include the impedance discontinuities and the crosstalk. In this paper, we discuss the bump pitch, trace layout pattern, layer define, copper roughness, low loss material, ball size and pitch to improve performance in the aspects of insertion loss, return loss and crosstalk for high speed SerDes application on flip chip package substrate. We scan the gap size of via pad which contributes the impedance discontinuity thus impacts signal integrity. Die bump and BGA pin assignments are the other two key factors in cause of crosstalk.