A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR

This article presents a low-power (LP), compact, wideband (WB) low-noise transconductance amplifier (LNTA)-first receiver (RX) designed for software-defined radios (SDRs). It comprises the LNTA, frequency divider, mixer, and trans-impedance amplifier (TIA). The LNTA utilizes a common gate (CG)-common source (CS) structure without on-chip inductors and incorporates gm-boosting and current reuse techniques to effectively reduce power consumption. A novel noise-canceling (NC) strategy is proposed to break the inherent tradeoff between input impedance matching, noise figure (NF), and gain. The divider adopts a windmill structure based on NAND gates, while 25% duty-cycle quadrature clocks drive the double-balanced passive mixer. The third-order filtering TIA is based on a three-stage pseudo-differential operational transconductance amplifier (OTA). It implements $RC$ and feedforward (FF) compensation techniques to attain a 3.25-GHz unity gain loop bandwidth (BW) and 68-dB loop gain. Fabricated in a 40-nm LP CMOS technology, the chip features 38-dB conversion gain, 50-MHz baseband (BB) BW, 3.5-dB NF, and in-band (IB) output third-order intercept point of up to 40 dBm. The RX operates over a frequency range of 0.1–5.5 GHz. It consumes 36 mW of static power in the RX signal path and 15 mW of dynamic power in the local oscillator (LO) path at 5 GHz. The core area is only 0.1 mm2.

I. Introduction

Software-defined radios (SDRs) [1], cognitive radios [2], and multi-standard applications [3] prefer wideband (WB) receivers (RXs) owing to their advantageous characteristics of flexibility and low cost. The Sub-6-GHz band is occupied by various communication protocols, and the spectrum is highly congested. WB RXs operating in this band face interference and blocker issues, primarily due to the absence of radio frequency (RF) filtering, which places high demands on the linearity of the RX front end [4].