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CAD Tools Pathway in Hardware Security | IEEE Conference Publication | IEEE Xplore

CAD Tools Pathway in Hardware Security


Abstract:

In modern computer devices, System-on-Chip (SoC) technology is used to design hardware components. The most sensitive assets of a SoC design are the encryption key, confi...Show More

Abstract:

In modern computer devices, System-on-Chip (SoC) technology is used to design hardware components. The most sensitive assets of a SoC design are the encryption key, configuration settings, and data stored on the device. As the semiconductor industry has become more globalized, there is an increased risk of unauthorized access to SoC assets in light of the outsourcing of the design process and the integration of third-party intellectual property (3PIP). There are significant security concerns when using 3PIP from different vendors since any threats may be inserted into the SoC design by an attacker. The designer must add IP countermeasures to the SoC to protect it from design flow vulnerabilities. To ensure the security and trustworthiness of IPs and SoC designs, they must be validated as security assets. Security issues in modern designs have become more challenging due to their complexity, and existing tools cannot resolve them. Security concerns may not be considered when designing tools optimized for area, power, and performance. To address security issues in the SoC design process, computer-aided design (CAD) tools and techniques are being developed to assess potential threats and detect security vulnerabilities. By addressing each vulnerability in the SoC design flow, these CAD tools automate security assessments as well as validate preferred metrics. In this paper, we explore the state-of-the-art of CAD tools usage in hardware security verification and validation. Here, we present the systematic utilization of CAD tools in the SoC design lifecycle, including their strengths and weaknesses. Finally, the paper concludes with an assessment of where we are with current research and directions for future research.
Date of Conference: 06-10 January 2024
Date Added to IEEE Xplore: 02 April 2024
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Conference Location: Kolkata, India

I. Introduction

The Internet of Things (IoT) has become a part of our daily lives, and embedded devices and Internet-of-things devices form a significant part of that world. Systems-on-chips (SoCs) are used across a wide range of applications, including smart consumer electronics, military and aerospace solutions. As digital convergence has developed over the last four decades, integrated circuits have become functionally sophisticated at mass-market prices. As digital convergence has developed over the last four decades, integrated circuits have become functionally sophisticated at mass-market prices. Fig. 1 shows that the number of IoT devices is rising to 30 billion in 2020, which is compared to a population of 8 billion which means that each person has four devices on average. With the rapid growth in speed and shrinkage in the size of VLSI technology, designers of VLSI system-on-chips face enormous challenges. Consequently, a single chip includes billions of transistors and digital/analog circuits. Microelectronics devices are combined into a single system-on-a-chip. System-level architectures in modern electronic devices have led to profound technological development in the semiconductor industry. It is mainly the goal of a SoC to design and build a system by integrating predesigns of hardware and software blocks and this is referred to as intellectual property (IP) in its collective form. In the context of SoC design, the behavior of a design occurs when IPs are operated and IP interface providers communicate. The implementation of SoC designs is not a straightforward process, and many challenges arise in fitting SoC designs into tight time-to-market windows.

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