Evaluation of Novel 16-Bit Vedic Multiplier Using Carry Look Ahead Adder for High Speed and Low Area in Comparison with Carry Select Adder

This research evaluates a unique carry look ahead adder (CLA) 16-bit Vedic multiplier's efficiency. Optimise speed and space utilisation and compare it to the standard carry select adder (CSA) design. Two sets of samples were tested to compare the carry select adder (CSLA) and unique carry look ahead adder. The first group included 10 CSLA samples and the second 10 CLA samples. ModelSim and VHDL were used for the evaluation. Propagation delay and power consumption were the main design evaluation criteria. The CSLA and CLA simulation results were obtained by running two sets of 10 samples each. Power utilisation was calculated using G-power with a 95% confidence interval. After the simulation, the data were analysed to determine each creative design's pros and cons. Analysis of both systems' propagation delay and power consumption provided crucial performance insights, helping choose the best design for certain applications. Results: The CLA had an average propagation delay of 15.5 ns and the CSLA 20.7 ns. The CLA used 2.4 mW and the CSLA 3.6 mW. A low p-value of 0.001 indicates statistical significance (p<0.05). Conclusion: The CLA performs better for fast-processing, low-power workloads. Thus, the unique CLA adder should be considered for use in high-performance digital circuits.