Reliability Assessment of 2.5D Module using Chip to Wafer Hybrid Bonding

Wafer to wafer hybrid bonding has been established to form fine pitch interconnections for high density I/O applications [1], [2]. However, this approach has limitation that demands same interconnects layout and same chip sizes for both wafers. In addition, yield of the bonded wafer is affected severely from the individual yield of the wafer and the location of the chip with good yield. Chip to Wafer hybrid bonding is an attractive approach to mitigate the yield issue and the different design aspect from the chip and the wafer. However, it is not an easy approach as it demands absolute cleanliness of bonding surfaces for both chip and the wafer throughout the assembly processes. This article demonstrates reliability assessment of chip to wafer bonding approach. A good yield of chip to wafer hybrid bonding was obtained and the bonding interface remained intact throughout the thermal cycling tests and moisture sensitive test.

Introduction

Chip to wafer hybrid bonding is getting more and more adopted by the industry in handling devices with ultra-fine pitch below 10 μm. Challenges such as oxide planarization, surface activation impact on surface roughness and contact angle, copper oxide’s thickness, and high bonding accuracy In addition, bonder’s cleanliness, compatibility of the assembly material such as dicing tape in the surface activation process, stringent Cu dishing magnitude and uniformity impact the yield of the Hybrid bonding. Dicing induced particles are encountered for mechanical blade dicing approach and need to be mitigated in the hybrid bonding process [3], [4], [5].