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Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation | IEEE Conference Publication | IEEE Xplore

Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation


Abstract:

This paper proposes a clock buffer with compensator technology to achieve low-jitter design in the digitally controlled oscillator (DCO). The compensator consists of a PM...Show More

Abstract:

This paper proposes a clock buffer with compensator technology to achieve low-jitter design in the digitally controlled oscillator (DCO). The compensator consists of a PMOS transistor and a MOS capacitor. The compensator that provides the opposite sensitivity to the delay cell is connected to the node between each delay cell. The compensated DCO has a reduced jitter of approximately 12.7-ps (peak-to-peak) based on the 3-GHz output frequency under ±0.1% VDD noise.
Date of Conference: 28-31 January 2024
Date Added to IEEE Xplore: 19 March 2024
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Conference Location: Taipei, Taiwan

References

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