Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs

We propose a multicorner multistage timing analysis prediction framework using a generalized linear model with latent features. We then further improve such methods using kernel trick extension, transfer learning with knowledge from previous designs, and multioutput feature engineering to deliver state-of-the-art (SOTA) prediction accuracy with very limited training data. Most importantly, our method is equipped with a Bayesian decision strategy to deliver reliable predictions with accuracy close to 100%, pushing the frontier of the machine-learning-based static timing analysis (STA) for practical implementation in the industry environment, where reliability is highly desired. Experimental results show that the accuracy of our proposed method outperforms the SOTA competitors by up to 4x and can improve prediction accuracy to 100% with little extra STA executions.

I. Introduction

In order to guarantee the timing yield, chip designers resort to static timing analysis (STA) to evaluate the timing correctness under different process corners (PCs) [1]. Thanks to the fast speed and reliability of STA, it has been widely used for timing verification in the past few decades. As the technology node scales down into the nanometer regime, the process, voltage, and temperature (PVT) variations impact chip performance significantly [2]. As a result, the number of process corners increases drastically with the technology node scaling [3], [4]. For instance, the number of process corners rockets up to over 100 in the 20-nm technology node and below [5]. The explosion of process corner count presents a challenge for traditional STA—extremely high-computational cost. Even worse, the conventional physical design goes through synthesis, floorplan, power plan, placement, clock synthesis, routing, and engineering change order (ECO) optimizations. Each stage requires extensive timing simulations to pinpoint the timing failure as early as possible. Therefore, STA has become an ever-increasing time-consuming procedure in modern chip timing verification.