VIB: A Versatile Interconnection Block for FPGA Routing Architecture

Routing architecture has a large impact on the FPGA performance and area. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs). There are also input crossbars inside the logic blocks (LBs). Muxes with high fanins are used to implement the intra- and inter-cluster connections. In the previous researches, CBs, SBs and input crossbars are designed separately which may miss some potential optimization spaces to trade off area, delay and routability. Besides, it is hard to model the complex routing architecture in commercial FPGAs. In this paper, we propose a novel tile-based routing architecture, versatile interconnection block (VIB) which replaces the CBs, SBs and input crossbars to alleviate this problem. All the routing resources are included in the VIBs which are based on two level mux topology used in many commercial FPGAs. Six parameters are proposed to describe the VIB architecture. In addition, VTR 8 is enhanced to support the proposed VIB architecture. Then, we compare the proposed architecture with the latest work of two level mux design. Experimental results show that the proposed VIB architecture can achieve 18.9% improvement on the routing area, 2% improvement on the routability and 16.6% improvement on the area-delay product with VTR benchmarks.