Limits to the Energy Efficiency of CMOS Microprocessors

CMOS microprocessors have achieved massive energy efficiency gains but may reach limits soon. This paper presents an approach to estimating the limits on the maximum floating point operations per Joule (FLOP/J) for CMOS microprocessors. We analyze the three primary sources of energy dissipation: transistor switching, interconnect capacitances and leakage power. Using first-principles calculations of minimum energy costs based on Landauer’s principle, prior estimates of relevant parameters, and empirical data on hardware, we derive the energy cost per FLOP for each component. Combining these yields a geometric mean estimate of 4.7 × 10¹⁵ FP4/J for the maximum CMOS energy efficiency, roughly two hundred-fold more efficient than current microprocessors.

I. Introduction

Driven by Moore’s law and Dennard scaling, digital Complementary Metal-Oxide Semiconductor (CMOS) devices have seen massive improvements in energy efficiency over the past few decades. This is perhaps best illustrated by Koomey’s Law [1] , which states that the Floating Point Operations (FLOP) per Joule dissipated doubled once every 1.5 years between 1946 and 2000 [1] , and every 2.7 years post-2000 [2] . More recently, [3] finds that GPUs with float32 number formats have had an energy efficiency doubling time of about 2.7 years over the last 15 years. But how far can these energy efficiency improvements continue before technology scaling hits physical limits?