A 1.3–1.7-GHz Q-Enhanced Resonator-Based High-IF Bandpass Filter With 1.5%–67% Tunable Fractional Bandwidth in 65-nm CMOS Process

In this article, a tunable four-stage high-intermediate-frequency (IF) bandpass filter (BPF) chip using inductors with a $Q$ compensation digital resistor array (QCDRA) is presented. The high-IF BPF intends to filter out-of-band spurs and distortions for radio frequency analog-to-digital converter (RF-ADC) or RF digital-to-analog converter (RF-DAC), which leverages programmable $Q$ -enhanced inductors to achieve ultrawide programmable bandwidth. The fabricated filter center frequency can be programed from 1.3 to 1.7 GHz with a 50-MHz resolution, which also supports a tunable signal passband from 25 to 1000 MHz with 25-MHz frequency step, equivalent to a 1.5%–67% tunable fractional bandwidth when centering at 1.5 GHz. The BPF exhibits < 50-ns signal bandwidth program settling time, suitable for agile radio applications. To ensure an accurate filtering, a three-point calibration scheme is proposed to auto-calibrate filter response due to temperature variations. The high-IF BPF chip is fabricated in a 65-nm bulk CMOS process with 80-mA current consumption, which achieves a 150.94-dB normalized dynamic range (DR). To the authors’ best knowledge, this high-IF BPF has demonstrated the widest fractional bandwidth programmability.