A-236.5dB Jitter-FoM Dual-Path RO-PLL With Improved Supply Sensitivity

In this paper, we propose a compact Ring Oscillator (RO) based PLL with a dual-path architecture for small loop filter area and a RO design with Kvdd compensation to reduce 38dB supply sensitivity. The proposed dual-path PLL was implemented in 55nm CMOS. In post-layout simulation and MATALB, it achieves rms jitter of 0. S44ps with 3.1mW power, leading to a FoMjitter of −236.5dB while occupying 0.0084mm2 chip area.