Design of Digital Phase Interpolator for 6.25Gbps CDR Circuit

For high-speed serial interface application, a digital phase interpolator(PI) for 6.25Gbps clock data recovery circuit is designed. The digital PI consisted of two groups of inverter arrays, with a digital signal controlling the number of gating of the inverter array to achieve the phase adjustment function similar to analog PI. Additionally, an 8-phase divider with reset function has been designed to provide 8-phase input clocks with the correct phase relation to the digital PI. The digital PI has been implemented using TSMC 40nm process, with a layout area of 53um*23um Post-simulation results show that, at an operating speed of 6.25 Gbps, the output clock jitter is only 7.66ps, representing less than 0.15 UI, and with a low power consumption of only 0.59 mW.

I. Introduction

With the rapid popularization of 5G technology, the amount of data transmitted between systems has rapidly increased, and the speed of data transmission through system interfaces has become a key factor hindering the performance improvement of systems. As a result, high-speed serial data transmission systems (SerDes) have received more and more attention as the primary technology for data transmission, thanks to their anti-interference capabilities and low power consumption. The SerDes receiver circuit needs to recover the correct signal from the distortied signal that results from transmission through the channel. This process is primarily implemented by clock data recovery (CDR).