Introduction
Noise caused in electronic receivers inherently limits the system sensitivity, which is why most receivers use a low-noise amplifier (LNA) at an early stage of the receiver in order to keep the degradation of the signal-to-noise ratio as low as possible. When ultraweak electromagnetic signals, such as radio-astronomical signals in
Lowest cryogenic noise temperatures (
Future cryogenic systems, such as radio astronomical phased arrays or superconducting quantum computers, will need to scale the number of channels and, consequently, the number of cryogenic amplifiers for performance enhancement. Especially for quantum computing, it is expected that the number of physical qubits will need to be scaled to approximately one million in order to achieve a useful fault-tolerant quantum computer (“quantum supremacy”) [3], [4], [5]. Even with frequency-domain multiplexing, the number of readout HEMT amplifiers will need to scale proportional to the number of qubits.
Currently, transmon qubits are read out in
Monolithic microwave-integrated circuits (MMICs) might be an alternative to hybrid amplifiers, since they inherently offer a much smaller footprint, which would help to overcome the size limitations of hybrids. In addition, multichannel or multifunctional chips could be realized for a very high integration level on the 4-K stage. However, current monolithic LNAs do not achieve the same noise and dc-power (
This article deals with the design and characterization of LNA MMICs dedicated to cryogenic ultralow-noise operation. An advanced 50-nm mHEMT technology optimized for cryogenic low-noise performance [10] is used for best noise. An accurate transistor small-signal and noise model working down to cryogenic temperatures is available [11] and allows to set up precise circuit simulations at cryogenic temperatures, which is used to fine-tune circuit parameters for cryogenic operation. Two LNA MMICs are presented: a two-stage design targeting
This article is structured as follows: The 50-nm mHEMT technology is briefly presented in Section II. In Section III, design strategies dedicated to monolithic ultralow-noise amplifier design with low-power consumption at cryogenic temperatures are discussed. The actual LNA MMICs and their design are presented in Section IV. Room temperature and cryogenic measurement results are provided in Section V. The presented LNAs are compared with the state of the art in Section VI. Section VII concludes this article.
50-nm mHEMT Technology
In this section, the 50-nm mHEMT technology used for MMIC design is briefly recapped [12]. The technology has been optimized for cryogenic ultralow-noise operation [10]. The epitaxial layer stack of the active devices is grown on 100-mm semi-insulating GaAs wafers starting with a linearly graded InAlGaAs metamorphic buffer layer to adapt the lattice constant from the GaAs to the InP value. The 2-D electron gas (2DEG) is confined in an In0.8Ga0.2As channel enclosed by In0.52Al0.48As barrier layers. The upper barrier layer is silicon delta-doped close to the barrier-to-channel edge. The epitaxial layer sequence is finalized by a saturation-doped In0.53Ga0.47As cap layer ensuring ohmic contacts with low resistance, which is important for low HEMT noise.
Wet-chemical recess etching with a succinic-based solution opens the cap layer. The gate is formed by electron beam lithography using a four-layer polymethylmethacrylat (PMMA) resist. The 50-nm gate is structured using electron beam evaporation of a PtTiPtAu sequence. The gate head of the T-gate is 170-nm long, and the entire gate is encapsulated in benzocyclobuten (BCB), which reduces parasitic capacitances compared with a classical SiN passivation. A second gate head consisting of the first metallization layer of the process is placed on top of the first gate head. The second gate head has a width of approximately 450 nm, which reduces the gate-line resistance significantly without a noteworthy increase in parasitic capacitance due to the increased distance to the semiconductor surface. A low gate resistance is a key to achieve low-noise transistors. Device isolation is achieved by mesa etching.
The process features two gold metallization layers, where the upper one is a thick plated layer that can be used to realize airbridges. Metal–insulator–metal (MIM) capacitors are formed by a 250-nm-thick SiN layer. NiCr thin-film resistors (TFRs) with an approximately temperature-independent sheet resistance of 50
Simplified wafer cross section to sketch the backend of line of the 50-nm process (dimensions are not true to scale).
Design Considerations for Cryogenic Low-Power LNA MMICS
Cryogenic LNA MMICs for large scale systems require lowest noise temperature, high gain, and low-dc-power consumption with sufficient input and output matching. Some of these requirements demand for a trade-off especially in an MMIC implementation. An investigation on how these demands can be fulfilled in an MMIC is given in the following.
It is well known that the first LNA stage mainly determines its noise performance, given that it provides sufficient gain [13]. Therefore, the design of the input stage is the key to achieve best noise performance. The lowest achievable noise temperature is given by the first-stage HEMT. Three noise parameters fully specify the noise of a device [14], [15], [16]: its optimal noise temperature (
Simulated noise paraboloids at 6 GHz of 50-nm mHEMTs in common-source configuration operated at
In general, on-chip networks on thin substrates are more lossy compared with thicker off-chip substrates, which can use wider lines to realize the same line impedance. Therefore, the input matching network needs to be designed as lean as possible in order to keep the losses low. An elegant way of transforming
It is found that matching with just a stub is only possible for devices with very large gate width. This implies several drawbacks: devices with larger unit gate width (
Choosing smaller gate width devices helps to limit the dc-power consumption and to use low
Another possibility to transform
The use of a series inductor has several advantages: it decreases
Following conclusions for circuit design can be drawn from the given input-stage investigation: the size of the HEMTs mainly determines the chips dc-power consumption, and low gate width devices are preferred in terms of dc power. However, especially in the first stage, the choice of
The investigation gives an insight into the circuit design process at a single frequency. However, besides noise matching also other related parameters need to be considered over a large bandwidth. Input matching needs to be achieved, which is typically done using inductive source degeneration. In the frequency band of interest, adding inductances at the source does only weakly influence
Cryogenic LNA MMICs
Two 50-nm mHEMT LNA MMIC are designed and investigated: LNA1 targets the
Both designs use inductors in airbridge technology for matching, which means the inductor turns formed of the thick plated metal layer are placed above the semiconductor surface in the air and are only attached to the wafer at selected points by small gold pillars. The thick plated metal layer ensures low resistance for low losses. Airbridge inductors have the advantage that the parasitic capacitance per inductor turn area is reduced compared with an inductor directly placed on the GaAs substrate due to the low
LNA1 uses only two stages in order to save the dc power of a third stage. This comes at the cost of lower gain. However, at least 30 dB of small-signal gain should be achievable with two stages. The design uses inductive source degeneration in both stages for simultaneous broadband input and noise matching. The inductances are realized as spiral airbridge inductors as well, in order to keep the added resistance at the HEMT source low for good noise performance. The first stage uses a
The four-channel version parallelizes four LNAs on a single MMIC. The dc-bias connections are routed on the output side of the LNAs. This is important, since the dc wiring needs to cross the RF lines, which can then only be realized using the first metallization layer with higher losses. At the output, the influence on the noise performance should be negligible. The dc lines distributing the drain current need to be built in the gold-plated layer in order to keep the voltage drop as low as possible, which is important to ensure that the HEMTs are operated in the same bias point in order to achieve the same performance for all channels. Based on the sheet resistance of the metal layers used, a worst-case estimation of the difference in the drain voltage provided to the different channels has been estimated. When the circuit is operated with 50 mA/mm, the maximal channel difference in the drain bias voltage should be less than 13.5mV. This is low enough to not expect large performance differences between the channels [10], [11]. The authors see this as a worst-case estimation based on very conservative measures and expect the voltage drop to be even lower in reality. Fig. 3 shows a simplified schematic of the four-channel LNA MMIC, with the single LNA1 channels grouped in boxes. Fig. 4 shows the chip micrographs of [Fig. 4(a)] the four-channel MMIC and [Fig. 4(b)] the stand-alone LNA (LNA1). Although the four-channel MMIC currently uses exactly four times the chip area of the stand-alone MMIC, integrating multiple channels in one MMIC helps to reduce the LNA footprint in an assembly. Furthermore, a second design generation could reduce the area per channel even further. Currently, the RF-to-RF pitch at input and output of the multichannel LNA MMIC is 930
Simplified schematic of the four-channel
Chip micrographs of (a) four-channel
LNA2 uses three stages, which has the advantage of higher amplifier gain even when the stages are driven with very low-dc-power consumption. However, a third stage will consume additional dc power compared with a two-stage design. An advantage of a three-stage design compared with a two-stage LNA is the better isolation between input and output. This eases the design, since the influence of the output stage on the input stage and vice versa is reduced. Furthermore, an additional degree of design freedom is obtained, which allows to use smaller gate width HEMTs per stage to reduce the dc power per stage.
The first-stage gate-width has been chosen to be
Chip micrograph of the three-stage extended
Both LNAs circuit parameters have been fine-tuned by setting up a cryogenic circuit simulation using the 50-nm mHEMT model published in [11], which combines a temperature-dependent small-signal model with an adapted Pospieszalski noise model [22]. Besides unconditional stability from the
Measurement Results
The LNA MMICs have been characterized both at room temperature and at cryogenic temperatures. Room temperature measurements have been performed on-wafer with a single probing contact per cell to obtain both S-parameter and noise temperature of the LNAs using a Keysight PNA-X vector network analyzer system with an integrated sensitive receiver and input tuner dedicated to noise measurements. The noise temperature has been measured using the vector-corrected cold-source method [26]. The noise receiver of the PNA-X is calibrated using a Keysight 346CK01 noise source, the one-port calibration at port2 used to determine the tuner reflection coefficients has been done using a Keysight N4694A 1.85-mm electronic calibration kit, and the two-port S-parameter calibration on probe reference plane is done on a Cascade 101-190C impedance standard substrate using load standards with trimmed resistance. Fig. 7 shows the measured and modeled S-parameters and noise of LNA1 at room temperature.
Measured (symbols) and simulated (lines) S-parameters (left) and effective noise temperature (right) of the
LNA1 achieves an average in-band (4–8 GHz) small-signal gain of 31 dB and an average in-band noise temperature of 67.1 K at room temperature. Both stages are biased at
Fig. 8 shows the measured S-parameters and noise temperature of all channels of the four-channel MMIC at room temperature. At 297 K, the maximal channel difference in average gain is less than 1 dB, and the difference in average noise between the channels is less than 0.7 K. As in a real multichannel receiver scenario, all channels are operated in parallel during the measurement. The measured performance of the multichannel MMIC at room temperature is comparable to the stand-alone version. The channel-to-channel isolation has been measured at room temperature on-chip. In order to provide decent matching, attenuator MMICs have been glued to the inputs and outputs that are not probed and connected with wire bonds. The four-channel MMIC is operated at
On-wafer S-parameter and noise temperature measurement and circuit simulation of the four-channel LNA MMIC at room temperature when operated at
Fig. 9 shows the measured S-parameters and noise temperature of LNA2 and the corresponding circuit simulation at 297 K. The MMIC achieves an average noise temperature of 60.5 K between 4 and 9 GHz with an average small-signal gain of 48.3 dB when operated at
On-wafer measured (symbols) and simulated (lines) S-parameter and noise temperature of the three-stage LNA MMIC at room temperature when operated at
Cryogenic measurements have been performed in a Lakeshore CRX-4K cryogenic probe station with a closed cycle helium refrigerator. Samples for testing are selected based on room temperature wafer mappings including dc, S-parameter, and noise temperature measurements to find representative devices. After wafer dicing, the devices under test (DUTs) are glued on a gold-plated copper disk using silver epoxy, which is similar to the module assembly process. The sample holder is mounted to the cooling stage with Apiezon N grease for proper thermal connection. S-parameters have been measured using a Keysight PNA-X vector network analyzer similar to the one used for room temperature testing. The cryogenic calibration at probe tip reference plane has been performed using a line–reflect–reflect–match calibration [27], [28], where the match resistors have been dc measured in order to achieve a highly accurate calibration. The cryogenic noise temperature has been measured in a second measurement step using the well-established cold attenuator measurement principle [29]. The principle has been adapted for cryogenic on-chip measurements with low measurement uncertainty using a 20-dB attenuator MMIC with integrated temperature sensor that is glued next to the DUT and connected via wire bonds according to [30], and a worst-case measurement uncertainty of ±1.4 K has been estimated. The cryogenic noise measurements have been performed using a Keysight N4000A noise source and an Agilent N8975A noise figure analyzer. Fig. 10 shows a micrograph of the assembled four-channel noise measurement setup.
Micrograph of the four-channel LNA MMIC assembly for on-chip noise temperature measurement. Four dedicated 20-dB attenuator MMICs (pink dashed boxes) are glued in front of the four-channel DUT (yellow dashed box) and connected to the four inputs with wire bonds (turquoise dashed box). Each attenuator MMIC occupies a chip area of
Fig. 11 shows the measured and simulated S-parameters and noise temperature of LNA1 at 10 K. LNA1 achieves an average small-signal gain of 31.5 dB and an average noise temperature of 3.2 K between 4 and 8 GHz at 10 K when operated at
Measured (symbols) and simulated (lines) S-parameters (left) and effective noise temperature (right) of the
Cryogenic S-parameter and noise temperature of all channels of the four-channel LNA MMIC when it is operated at best noise bias [
(a) Measured and simulated S-parameters and noise temperature of the four-channel
An investigation on how the power consumption of the four-channel MMIC can be further reduced has been made. Fig. 13 shows the measured S-parameters and noise of all channels of the multichannel LNA at 10 K when operated with an ultralow dc power of
(a) Measured S-parameters of the four-channel
Fig. 14 shows the measured and modeled S-parameters and noise temperature of LNA2 at 10 K when biased for optimal noise. LNA2 achieves an average noise temperature of 3.3 K between 4 and 9 GHz (2.9 K between 6 and 9 GHz) with an average small-signal gain of 44.5 dB between 4 and 9 GHz (43.3 dB between 6 and 9 GHz). The input matching is better than −9.5 dB from 4 to 9 GHz and better than −15 dB between 4.8 and 9 GHz. The output is matched better than −5 dB over the whole band, and between 5 and 9 GHz, matching is better than −10 dB. At optimal noise bias, 5.57 mW of dc power is consumed, which has been achieved by allowing a slightly higher bias current in the first stage and reduced bias currents in the remaining stages. It is believed that the higher first-stage drain current density and drain voltage needed in LNA2 to achieve best noise is a consequence of the lower first-stage gate width in combination with the higher source inductance network. Higher source inductance is needed for broadband matching introducing higher loss, which is gainwise compensated by using a slightly higher current density. The absolute first-stage current and, consequently, the dc power are still low, since the first-stage device gate width is smaller than in LNA1.
Measured (symbols) and simulated (lines) S-parameters (left) and effective noise temperature (right) of the three-stage extended
LNA2 has been measured with an ultralow-power consumption of 1.34 mW at 10 K, and the corresponding noise and gain measurements are provided in Fig. 15. An average gain of 35.4 dB between 4 and 9 GHz (34.7 dB between 6 and 9 GHz) is achieved at low-power operation. The average noise between 4 and 9 GHz is 4.4 K (4.0 K between 6 and 9 GHz) at ultralow-power consumption.
Cryogenic gain (red) and noise temperature (blue) measurements of the three-stage LNA MMIC when operated at an ultralow-dc-power consumption of 1.34 mW [
LNA1 achieves the lower noise temperature and also lower power consumption in low-power mode compared with LNA2. However, LNA2 offers higher gain, which is an advantage especially in low-power mode. The use of the three stages also helps to improve related circuit parameters as input and output matching. The noise performance and power consumption of LNA2 are also very low in both biasing modes. The four-channel MMIC does not have any disadvantages compared with the stand-alone chip, which demonstrates that such a high integration level can be handled at cryogenic temperatures. The presented four-channel MMIC could easily be extended to eight channels by mirroring the layout of this chip at its south edge.
State-of-the-Art Comparison
The proposed LNA MMICs are compared with the state of the art in Table I. The table is split into two groups: in the upper half, hybrid LNAs, which use external dedicated low-loss substrates for matching, are provided. The second part shows MMICs, and on the bottom, the results of this work (MMICs) are listed.
Hybrid LNAs still offer the best noise performance in
To the best of the authors’ knowledge, LNA1 provides the lowest noise temperature among
LNA2 uses a third stage to overcome the slight limitation in gain of LNA1 when it is operated with low power. The average noise performance of LNA2 is slightly higher, but it offers an even broader bandwidth with improved input and output matching. The power consumption in low-power mode is slightly higher compared with LNA1, which is a consequence of the third stage. The average noise performance is still better than values of other MMICs reported in the literature both when operated for low power and optimal noise. In low-power mode, the power consumption is lower than the ones provided in the literature for LNA MMICs. A gain of 35.4 dB is achieved with ultralow-power consumption of 1.34 mW.
Conclusion
In this article, monolithically integrated
Circuit design strategies for monolithic LNAs at cryogenic temperatures have been discussed in order to improve the noise performance and power consumption of LNA MMICs in
LNA2 achieves a broader bandwidth with improved matching, especially in the 5–9-GHz region, with 3.3-K average noise temperature and the highest gain (44.5 dB) among LNAs published in the literature. This is an advantage when LNA2 is operated with 1.34 mW of dc power, since 35.4 dB of gain and 4.4-K noise temperature are still achieved.
Although the noise performance of hybrid HEMT LNAs in
ACKNOWLEDGMENT
The authors would like to thank D. Meder for the assembly of the chips for the cryogenic measurements. They would also like to thank their colleagues from the Epitaxy and Technology Department, Fraunhofer Institute for Applied Solid State Physics (IAF), Freiburg im Breisgau, Germany, for excellent wafer growth and processing.