Knowledge Transfer Framework for PVT Robustness in Analog Integrated Circuits

Process, voltage, and temperature (PVT) variations in chip fabrication or operation pose a significant challenge to the robustness of analog integrated circuits. Existing design techniques for mitigating PVT variations involve analyzing offsets of DC operating points, but this approach often leads to compromises in circuit performance. To address this challenge, we developed a ‘PVT-Transfer’ framework to facilitate knowledge transfer with evolutionary design. Specifically, by cross-operating the circuit parameters under variations, design knowledge is transferred through parameter migration, thus enhancing the robustness of the resultant circuit. In addition, we leverage data-driven learning to discover potential similarities among PVT variations, thereby mitigating negative knowledge transfer. The PVT-Transfer Framework is evaluated on three integrated voltage references and compared with four state-of-the-art circuit sizing methods. Based on post-layout Monte-Carlo simulations, this framework is verified to offer superior performance to existing methods, yielding a 60% reduction in power consumption, an 80% increase in temperature resilience, and up to $70\times $ enhancement in the figure of merit. Further, it leads to a 60% reduction in the number of required circuit simulations and is suitable for parallel computation.

I. Introduction

Despite the tremendous progress of electronic design automation (EDA) so far, the design of an analog integrated circuit (IC) is still performed predominantly manually through precise calculations and repeated adjustments to transistor sizes. This process is inefficient and suboptimal due to the highly non-linear nature of analog circuits. Further, such a design outcome is often uncertain and is limited by the designer’s experience and knowledge, where the issue of performance deviations caused by process, voltage, and temperature (PVT) variations remains inadequately addressed in design automation [1], [2], [3], [4], [5]. Hence, analog EDA technology should ensure robustness and optimality under PVT variations [6], [7], [8].