Abstract:
This brief presents a 135ps dynamic range, 5.45ps effective resolution 2D Vernier time-to-digital converter for use in an all-digital phase-locked-loop. The matrix readou...Show MoreMetadata
Abstract:
This brief presents a 135ps dynamic range, 5.45ps effective resolution 2D Vernier time-to-digital converter for use in an all-digital phase-locked-loop. The matrix readout array limits the number of delay cells necessary by using all taps of the delay lines. A full calibration scheme is presented. It calibrates the system against PVT variations and maintains and favors a linear operation over achieving a specified resolution. The proposed architecture is fabricated in a 28nm CMOS technology and consumes 360 \pmb {\mu }\text{W} at 0.9V supply voltage and 55MS/s conversion rate.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Volume: 71, Issue: 3, March 2024)