Abstract:
In the constantly evolving field of multiplication architectures, the Karatsuba algorithm and its extensions have captivated the minds of researchers with their performan...Show MoreMetadata
Abstract:
In the constantly evolving field of multiplication architectures, the Karatsuba algorithm and its extensions have captivated the minds of researchers with their performance metrics. One such optimized design is the Overlap-free Karatsuba (OKA) algorithm which has emerged as an innovative architecture, specifically aimed at enhancing power, performance, and area (PPA) parameters. In this paper, we introduce a novel technique referred to as M-term Non-Homogeneous Hybrid Overlap-free Karatsuba polynomial multiplier (MNHOKA), which surpasses existing state-of-the-art (SOTA) designs, including Karatsuba multiplier (KA), M-Term Karatsuba-like multiplier (MKA), Composite M-term Karatsuba-like multiplier (CMKA), and Overlap-free Karatsuba multiplier (OKA), across various operand sizes. In this paper, a detailed analysis of the proposed MNHOKA and its corresponding M-Term Non-homogeneous Hybrid Karatsuba Algorithm (MNHKA) is presented, highlighting its performance improvements on both Cadence 45 nm process and the ZYNQ ZCU-104 FPGA board for popular bit widths. In ASIC implementations, MNHOKA achieves significant ADP improvements of 28.33%, 28.99%, 58.23%, and 11.95% for operand sizes of 128, 232, 282, and 750 bits, respectively, compared to the best-case SOTA design. Furthermore, our method yields lower power consumption. When comparing FPGA results of the proposed MNHKA design with the best-case SOTA works, ADP improvement of 22.72%, 16.10%, 2.52%, and 11.36% improvement was achieved for the respective bit-widths of 128, 232, 282, and 750 bits respectively. The advantages of the proposed MNHOKA, along with its equivalent MNHKA design variants, are evident in their superior hardware characteristics over existing SOTA designs. This research represents a significant step towards realizing efficient Cryptosystems in the immediate future. To foster further research and innovation, we have made the hardware design files freely available to the researchers and designer community.
Date of Conference: 06-08 November 2023
Date Added to IEEE Xplore: 22 December 2023
ISBN Information: