A Half-Bridge Gate Driver With Self-Adjusting and Tunable Dead-Time Modes for Efficient Switched-Mode Power Systems

The design of high-voltage (HV) switched-mode power systems (SMPSys) poses multiple challenges, such as minimizing the switching losses and preventing possible shoot-through currents, to achieve efficient and reliable operation. This article introduces a reconfigurable half-bridge gate driver (GD) for SMPSys, with an open-drain output configuration, electrostatic discharge self-protection, and two dead-time management modes to address these challenges. The first mode is an externally tunable fixed dead-time generator (FDTG) capable of achieving a wide dead-time range from 5 to 200 ns. The second mode is a self-adjusting dead-time generator (SDTG), designed to adapt to delay mismatches between the GD's channels, regardless of process, voltage, and temperature (PVT) variations, while minimizing dead-time and preventing cross-conduction. The GD was fabricated in an HV 0.18-μm silicon-on-insulator CMOS process technology, supporting a high-side floating bias voltage rail up to 100 V and occupying a core area of 0.285 mm². It was tested in a buck converter system using a gallium nitride (GaN)-based half-bridge with a switching frequency of 0.5 to 1 MHz. It achieves a total propagation delay of 11.4 ns and a minimum dead-time of 3.6 ns (3× smaller than state-of-the-art) using its SDTG mode. The system achieved a peak efficiency of 90.5% at an output load of 8 W. Notably, the SDTG mode improves the overall efficiency by up to 20% over the FDTG mode, specifically at higher switching frequencies, showing its effectiveness in enhancing the performance of SMPSys.