A DRAM Bandwidth-Scalable Sparse Matrix-Vector Multiplication Accelerator with 89% Bandwidth Utilization Efficiency for Large Sparse Matrix

Sparse matrix-vector multiplication (SpMV) plays a crucial role in diverse engineering applications, including scientific/engineering modeling, machine learning, and information retrieval, as depicted in Fig. 1 [5]. To efficiently store sparse matrices and minimize memory waste, the widely employed COO (Coordinate) compression format stores only the coordinates (row index, column index) of the non-zero elements in the matrix along with their corresponding values. However, the memory-intensive nature of SpMV operations, combined with irregular memory access patterns and limited data reuse resulting from the COO format, pose significant challenges for achieving high-performance implementations [6]. To assess the performance and efficiency of FPGA-based SpMV accelerators [1]–[4], which are typically optimized for specific hardware platforms, Bandwidth Utilization (BU) serves as a key metric for fair comparisons across different hardware specifications [6].