I. Introduction
The fast Fourier transform (FFT) is one of the most commonly used algorithms in digital signal processing applications such as radio astronomy [1] and wireless communications [2]. In wireless communications, future 6G systems will demand higher data rates [3]. In order to satisfy the demands of 6G, efficient hardware architectures are required [4] – [15]. There are three main types of FFT hardware architectures: Memory-based [13], [14], fully parallel [15] and pipelined [4] – [10]. Memory-based FFT architectures consist of one or more processing elements and several banks of memory. They process the FFT iteratively and can not receive new data while an FFT is being computed. Fully parallel FFT architectures are the direct implementation of the flow graph of an FFT algorithm. They obtain the maximum throughput but also require a large amount of resources to be implemented. Pipelined FFT architectures consist of a series of stages that include butterflies and rotators. They allow to process a continuous flow of data without requiring too many resources.