WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits

Extracting word-level functions from gate-level circuits is challenging and crucial in security, synthesis, and verification applications. State-of-the-art approaches identify subcircuits to match against a predefined library of components. However, they fail for highly-optimized arithmetic circuits due to the absence of intermediate word structures and the high complexity of verifying arithmetic functions. The challenge of learning arithmetic operations from gate-level netlists is posed in the 2022 ICCAD CAD Contest. This work tackles the challenge by devising and combining algebraic, statistical, and structural techniques into an operational flow for function extraction and simplification. Beyond the contest setting, our method also deals with circuits without their input-and output-pin information. Experiments on the contest benchmarks show that our method outperforms the winning teams in the contest in both the number of solved cases and the compactness of the extracted word-level expressions. Moreover, our method can effectively extract most word-level functions within 10 minutes.

I. Introduction

Extracting high-level information from low-level implementation can be beneficial and sometimes indispensable in the design flow of integrated circuits. E.g., the Layout Versus Schematic (LVS) problem [1] is essential in physical design verification. Also, extracting word-level functions from gate-level netlists can be important in applications such as hardware Trojan detection [2], intellectual property (IP) infringement verification [3], multiplier circuit verification [4], [5], engineering change order (ECO) [6], design debugging [7], circuit optimization [7], among others. While generating gate-level netlists from physical layout is well-studied [8], retrieving word-level functions from gate-level netlists remains challenging.