Power optimization in /spl Sigma//spl Delta/ ADC design

A power optimization method for sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converters (ADCs) is presented. System-level considerations are taken into account to maximize the peak signal-to-(noise+distortion) ratio (SNDR) versus power consumption. Both continuous-time (CT) and discrete-time (DT) loop filters are analyzed. The power consumption of CT and DT integrators is calculated and the best combination of CT/DT integrators is used. This concept is applied in designing a mixed CT/DT /spl Sigma//spl Delta/ ADC for telephony applications. The ADC has a power consumption of only 1.7 mW while operating with a single supply voltage of 1.8 V. A bandgap reference is integrated on-chip to reduce the number of external connections.