A Novel Network On Chip Architecture For FPGA Smart NIC

The public cloud is the backend of a massive and exponential growing percentage of online software services [1]. These services consume exabytes of storage, petabytes of network bandwidth, and millions of processor cores. The requirement for networking speeds has gone up by almost 10 times in the last few years. Software Defined Network policies of customers change rapidly in weeks or months so they required a solution that could provide software-like programmability while providing hardware like performance [3]. Field programmable gate array based smart network interface card or SmartNIC is the best-suited solution for this requirement. SmartNICs are pushing computation and therefore, acceleration to the edge of the network, freeing up server CPUs to work on more solutions focused on complex business-critical processing. Network on Chip is an integral part of this architecture which enables concurrent communication among multiple clients. We highlight limitations of traditional IP vendor Arteris Network On Chip architecture [5] and discuss novel Network On Chip architecture that was introduced to support high bandwidth requirement, crossbar connectivity across 30 unique sets of initiators and targets, handling traffic type of various protocols, end-end non-blocking architecture with 54 isolated logical paths, as part of architecture definition of 400 G Infrastructure Processing Unit or IPU solution for Cloud Service Providers under tight constraints of power and area targets.