Design and Performance Prediction of Ternary SRAM Cells Using GAA CNTFETS for Low Power Applications

The given work introduces a novel design of a low power 17 transistor ternary static random access memory (17T-TSRAM) cell that utilizes a 10nm gate all around carbon nanotube field effect transistor (GAA CNTFET). The proposed design aims to achieve higher speed, lower leakage power, and lower energy consumption. The design employs two 6T standard ternary inverters (STI) that are cross-coupled with differential write and single-ended read circuitry to form the proposed 17 Transistor(17T) TSRAM cell. The design is operated at a low supply voltage of 0.5 volts, which helps to minimize the overall power consumption. The accomplishment of the proposed design is evaluated by comparing it with existing designs that utilize 10nm and 32nm CNTFET verilog-A models. The results show that the proposed TSRAM design offers remarkable improvements in several key parameters like leakage power consumption, write delay, read delay, and PDP (Power-Delay Product), resulting in lower overall energy consumption. Overall, the proposed design of a low power 17T TSRAM cell using GAA CNTFET technology offers promising improvements in terms of energy efficiency and performance compared to existing designs.