Contents I. Introduction
As FPGA architectures increase in size and heterogeneity, even state-of-the-art placers [1]–[3] are facing scaling challenges with respect to runtime and quality-of-result. Large, complex designs can easily take hours, or even days, to place with no guarantee of post-routing closure. A primary reason for this situation is that traditional rule-based FPGA flows [1]–[3] are static; that is, they automatically apply the same core optimizations to all placement problems regardless of the features of the individual circuits. Though generally robust, this one-size-fits-all methodology can cause unneces-sary or potentially detrimental optimizations to be performed, adversely affecting runtime and solution quality. For example, the RippleFPGA placement flow [1] initially inflates the size of all blocks by 40% in preparation for resolving any congestion that might appear later in the placement flow. This strategy works well if the placement becomes congested. However, if the placement does not become congested, the original decision to inflate blocks often results in increased wiring cost, which can prevent post-routing closure. Moreover, initially inflating blocks only to deflate them later in the placement flow unnecessarily adds to what are already long placement runtimes. Another example occurs in the GPlace3.0 placement flow [3], where the analytic solver first produces a placement solution with minimized wirelength before measuring congestion, inflating blocks, and re-optimizing. For uncongested circuits applying the secondary optimization step adds significant runtime without necessarily improving quality-of-result.
