Accelerated Design of CNN Convolutional Calculator Based on Verilog

As convolutional neural networks (CNN) are widely used in daily life, both the network algorithm itself and the hardware facilities that carry the network are under higher requirements. Therefore, this paper first analyses the structure of convolutional neural network, and obtains the relationship between input and output of each convolutional layer and the calculation process. By analysing the computational process of convolutional neural networks, the potential parallelism in neural networks is explored. Then, the accelerated design is carried out for the convolutional computing channel, the main body of convolutional neural network. Finally, according to Verilog simulation, it is concluded that the improved adder structure realized by improved adder has excellent overall performance, reducing the power consumption (without considering IO consumption), LUT consumption and delay to 58.8%, 84.5% and 52.1% respectively, compared with the full adder structure implemented through ripple carry adder.