Abstract:
In 2022, IBISWorld reported that ∼93% of American households own at least one computer. In fact, most of us are very much plugged into either our smartphones or computers...Show MoreMetadata
Abstract:
In 2022, IBISWorld reported that ∼93% of American households own at least one computer. In fact, most of us are very much plugged into either our smartphones or computers or both for a significant portion of our lives [1]. Every one of these devices is powered by billions of transistors; the most powerful desktop CPU today, Intel’s 13th-generation Raptor Lake, is powered by ∼12 billion transistors. Just to give some context into the enormity of this number, the first transistor was developed by J. Bardeen and W. Brattain in 1947, 75 years ago (Figure 1). Intel’s cutting-edge Pentium 4 microprocessor introduced at the dawn of the 21st century in 2000 contained 42 million transistors. Today’s microprocessors have ∼300 times as many transistors as they did, just about 20 years back. While both the invention and commercialization of transistors were responsible for the birth of Silicon Valley, the explosive scaling and evolution of transistor technology have both fueled growth far beyond that of Silicon Valley. Advances from medical innovations to highly complex simulations to sophisticated artificial intelligence all have been made possible in one way or another by the evolution of transistor technology in the last few decades.
Published in: IEEE Solid-State Circuits Magazine ( Volume: 15, Issue: 3, Summer 2023)
References is not available for this document.
Contents Select All
1.
“Percentage of households with at least one computer,” IBISWorld, Manhattan, NY, USA, Aug. 2022. [Online]. Available: https://www.ibisworld.com/us/bed/percentage-of-households-with-at-least-one-computer/4068/
2.
“Inventing the transistor–CHM revolution,” Computer History Museum, Mountain View, CA, USA. [Online]. Available: https://www.computerhistory.org/revolution/digital-logic/12/273
3.
S. Chih-Tang, “Evolution of the MOS transistor-from conception to VLSI,” Proc. IEEE, vol. 76, no. 10, pp. 1280–1326, Oct. 1988, doi: 10.1109/5.16328.
4.
W. F. Brinkman et al., “A history of the invention of the transistor and where it will lead us,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1858–1865, Dec. 1997, doi: 10.1109/4.643644.
5.
J. A. Fleming, “Instrument for converting alternating electric currents into continuous currents,” U.S. Patent 803 684, Nov. 7, 1905.
6.
J. E. Lilienfeld, “Method and apparatus for controlling electric currents,” U.S. Patent 1 745 175, Jan. 28, 1930.
7.
J. Bardeen and W. Brattain, “Three-electrode circuit element utilizing semiconductor materials,” U.S. Patent 2 524 035, Oct. 3, 1950.
8.
M. Riordan and L. Hoddeson, Crystal Fire: The Invention of the Transistor and the Birth of the Information Age. New York, NY, USA : Norton, 1997.
9.
W. Shockley, “Circuit element utilizing semiconductive material,” U.S. Patent 2 569 347, Sep. 25, 1951.
10.
G. E. Moore, “The role of Fairchild in silicon technology in the early days of ‘Silicon Valley,’ ” Proc. IEEE, vol. 86, no. 1, pp. 53–62, Jan. 1998, doi: 10.1109/5.658759.
11.
J. Hoerni, “Method of manufacturing semiconductor devices,” U.S. Patent 3 025 589, May 20, 1962.
12.
R. N. Noyce, “Semiconductor device-and-lead structure,” U.S. Patent 2 981 877, Apr. 25, 1961.
13.
J. S. Kilby, “Miniature semiconductor integrated circuit,” U.S. Patent 3 115 581, Dec. 24, 1963.
14.
K. Dawon, “Electric field controlled semiconductor device,” U.S. Patent 3 102 230, Aug. 27, 1963.
15.
G. E. Moore, “Progress in digital integrated electronics,” in Proc. IEEE Int. Electron Devices Meeting, 1975, pp. 11–13.
16.
R. H. Dennard et al., “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. 9, no. 5, pp. 256–268, Oct. 1974, doi: 10.1109/JSSC.1974.1050511.
17.
K. Mistry et al., “Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology,” in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 2004, pp. 50–51, doi: 10.1109/VLSIT.2004.1345387.
18.
V. Chan et al., “Strain for CMOS performance improvement,” in Proc. IEEE Custom Integr. Circuits Conf., 2005, pp. 667–674, doi: 10.1109/CICC.2005.1568758.
19.
J. Faricelli, “Layout-dependent proximity effects in deep nanoscale CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., 2010, pp. 1–8, doi: 10.1109/CICC.2010.5617407.
20.
A. Loke et al., “Analog/mixed-signal design challenges in 7-nm CMOS and beyond,” in Proc. IEEE Custom Integr. Circuits Conf., 2018, pp. 1–8, doi: 10.1109/CICC.2018.8357060.
21.
C. K. Maiti and T. K. Maiti, Strain-Engineered MOSFETs. Boca Raton, FL, USA : CRC Press, 2013.
22.
P. Bai et al., “A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell,” in Proc. IEEE Int. Electron Devices Meeting, 2004, pp. 657–660, doi: 10.1109/IEDM.2004.1419253.
23.
K. Mistry et al., “A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging,” in Proc. IEEE Int. Electron Devices Meeting, 2007, pp. 247–250, doi: 10.1109/IEDM.2007.4418914.
24.
C. Auth et al., “45nm high-k + metal gate strain-enhanced CMOS transistors,” in Proc. IEEE Custom Integr. Circuits Conf., 2008, pp. 379–386, doi: 10.1109/CICC.2008.4672101.
25.
S. Natarajan et al., “A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array,” in Proc. IEEE Int. Electron Devices Meeting, 2008, pp. 1–3, doi: 10.1109/IEDM.2008.4796777.
26.
C. Auth et al., “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in Proc. IEEE Int. Electron Devices Meeting, 2008, pp. 131–132, doi: 10.1109/VLSIT.2012.6242496.
27.
J. P. Colinge et al., “Silicon-on-insulator ‘gate-all-around device,’ ” in Proc. Int. Tech. Dig. Electron Devices, 1990, pp. 595–598, doi: 10.1109/IEDM.1990.237128.
28.
A. Agarwal et al., “Gate-all-around strained Si0.4Ge0.6 nanosheet PMOS on strain relaxed buffer for high performance low power logic application,” in Proc. IEEE Int. Electron Devices Meeting, 2020, pp. 2.2.1–2.2.4, doi: 10.1109/IEDM13553.2020.9371933.
