Abstract:
Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-...Show MoreMetadata
Abstract:
Mathematically secure cryptographic algorithms leak significant side-channel information through their power supplies when implemented on a physical platform. These side-channel leakages can be exploited by an attacker to extract the secret key of an embedded device. The existing state-of-the-art countermeasures mainly focus on power balancing, gate-level masking, or signal-to-noise (SNR) reduction using noise injection and signature attenuation, all of which suffer either from the limitations of high power/area overheads, throughput degradation or are not synthesizable. In this article, we propose a generic low-overhead digital-friendly power SCA countermeasure utilizing a physical Time-Varying Transfer Function (TVTF) by randomly shuffling distributed switched capacitors to significantly obfuscate the traces in the time domain. We evaluate our proposed technique utilizing a MATLAB-based system-level simulation. Finally, we implement a 65nm CMOS prototype IC and evaluate our technique against power side-channel attacks (SCA). System-level simulation results of the TVTF-AES show \sim 5000\times minimum traces to disclosure (MTD) improvement over the unprotected implementation with \sim 1.25\times power and \sim 1.2\times area overheads, and without any performance degradation. SCA evaluation with the prototype IC shows 3.4M MTD which is 500\times greater than the unprotected solution.
Published in: IEEE Open Journal of Circuits and Systems ( Volume: 4)