High-Speed all-GaN Gate Driver with reduced power consumption

This paper presents a gate driver topology designed in a GaN on Si technology to be implemented on the same substrate with a 650-V, $500-\mathrm{m}\Omega$ power GaN switch. The driver consists of three buffer stages, three anti-cross conduction networks, two level shifters, and three bootstrap capacitors. Simulations of the proposed GaN driver are presented and a comparison with the conventional solution, assuming the same static current consumption, is provided. The proposed circuit not only solves cross-conduction problems, which are crucial for the limitation of undue dynamic power consumption, but it is also aimed at limiting static current consumption by using a bootstrap technique. Simulations show that the power GaN transistor driven by a 6-V, 2.5-MHz PWM signal with 50% duty cycle through the proposed driver, reaches a nominal switching speed as high as 50 V/ns at 27 °C, with an average current consumption of about 1 mA, over the entire range of temperature from −40 °C to 150 °C.