2.5D MCM (Multi-chip Module) Technology Development for Advanced Package

2.5D silicon interposer packages have been widely adopted for high-end applications such as datacenter, networking, and artificial intelligence. To meet the increasing demand for higher performance and greater bandwidth, the die and package sizes have been increasing due to the need for higher levels of device integration. As the package size increases, chip-to-package interaction (CPI) will become more challenging to manage. The main challenges with large 2.5 devices are warpage, C4 bump integrity, underfill cracking, and mold compound delamination caused by interposer corner stress. In our study, package warpage and reliability of a chip-on-wafer-on-substrate (CoWoS) multi-chip module (MCM) package with two 1.5X reticle interposers and a package size of 85mm×85 mm were investigated. The coefficient of thermal expansion (CTE) mismatch between different package materials can cause warpage and induce mechanical stresses that can lead to bump cracks, underfill delamination/cracking, and other failures in the package. We will discuss package design methods to reduce interposer die stress to enhance package reliability. By using finite element stress analysis to optimize the device layout, C4 bump standoff height, and interposer structure, large size 2.5D MCM packages were developed and evaluated with reliability testing.

I. Introduction

The growing demands in high performance computing and artificial intelligence are fueling the development of advanced packaging solutions for high performance devices. 2.5D packages with through-silicon via (TSV) interposers have emerged as an attractive packaging solution for heterogenous integration. CoWoS technology enables high levels of integration, improved electrical performance, and high transmission rates. By using TSV interposers to integrate the system-on-chip (SoC) and high bandwidth memory (HBM), system performance can significantly improve because the memory is moved much closer to the logic die resulting in shorter time delays and lower energy consumption.