Abstract:
The operational amplifier is a key building block in analog systems. However, the design process of the operational amplifier is time consuming and heavily depends on eng...Show MoreMetadata
Abstract:
The operational amplifier is a key building block in analog systems. However, the design process of the operational amplifier is time consuming and heavily depends on engineers’ experiences. This article presents OPAMP-Generator, an analog operational amplifier generator, which automates the full design flow from user-defined specifications to GDSII layout without human intervention. OPAMP-Generator includes behavioral-level topology optimization, efficient sizing algorithm based on the classical {g_{m}/I_{d}} design methodology, and automated layout generation. The behavioral-level description of the opamp is represented by the directed acyclic graph (DAG) and a customized variational graph autoencoder is proposed to embed the discrete graph representation into a low-dimensional continuous space. The topology of the opamp can thus be optimized in the latent space, which greatly improves the optimization efficiency. The sizing algorithm based on {g_{m}/I_{d}} methodology can guarantee the quality of transistor-level circuit implementation. The constraints of the layouts can be naturally derived from the topology level, which facilities the automatic generation of layouts. Experimental results demonstrate that our proposed method can efficiently synthesize operational amplifiers with competitive performances compared to manual designs.
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 42, Issue: 12, December 2023)
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- IEEE Keywords
- Index Terms
- Automatic Generation ,
- Design Process ,
- Design Methodology ,
- Latent Space ,
- Optimal Efficiency ,
- Directed Acyclic Graph ,
- Variational Autoencoder ,
- Topology Optimization ,
- Design Flow ,
- Circuit Implementation ,
- Manual Design ,
- Objective Function ,
- Decoding ,
- Optimization Method ,
- Behavioral Level ,
- Edge Weights ,
- Design Space ,
- Discrete Space ,
- Graph Convolutional Network ,
- Device Size ,
- Bilevel Optimization ,
- Analog Circuits ,
- Bilevel Optimization Problem ,
- Gaussian Process Model ,
- Transistor Size ,
- Acquisition Function ,
- Amplification Stage ,
- Design Specifications ,
- Circuit Size ,
- Automated Synthesis
- Author Keywords
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Automatic Generation ,
- Design Process ,
- Design Methodology ,
- Latent Space ,
- Optimal Efficiency ,
- Directed Acyclic Graph ,
- Variational Autoencoder ,
- Topology Optimization ,
- Design Flow ,
- Circuit Implementation ,
- Manual Design ,
- Objective Function ,
- Decoding ,
- Optimization Method ,
- Behavioral Level ,
- Edge Weights ,
- Design Space ,
- Discrete Space ,
- Graph Convolutional Network ,
- Device Size ,
- Bilevel Optimization ,
- Analog Circuits ,
- Bilevel Optimization Problem ,
- Gaussian Process Model ,
- Transistor Size ,
- Acquisition Function ,
- Amplification Stage ,
- Design Specifications ,
- Circuit Size ,
- Automated Synthesis
- Author Keywords