An Integrated System Scaling Solution for Future High Performance Computing

Transistor and system parallel tracks scaling will drive the scaling trends in semiconductor Performance, Power, Area/Formfactor, and Cost (PPAC). System scaling includes 3D/2.5D wafer level integration and heterogeneity. 3D Fabrics
^TM
scaling continues with system vertically scaling up, laterally scaling out, and interconnection pitch scaling in, all significantly contribute to system PPAC optimization. Latest 3D Fabrics pitch scaling are demonstrated for the first time. Another important scaling trend will be discussed is to incorporate in-package photonics heterogeneous integration, for PPAC scaling. 3DFabrics classical scaling, and heterogeneous photonics integration are the two pillars for future system scaling.