Abstract:
A product-ready L2 cache (L2C) design based on 6T ultra-dense SRAM cells with novel circuits capable of boosting word-line, cell, and, bit-line supplies independently usi...Show MoreMetadata
Abstract:
A product-ready L2 cache (L2C) design based on 6T ultra-dense SRAM cells with novel circuits capable of boosting word-line, cell, and, bit-line supplies independently using single supply and metal coupling capacitance is demonstrated for the first time in 5nm technology. A metal short detection circuit is provided to increase the robustness of the design. Hardware data shows that L2C operates with a minimum supply of 0.57V and reaches a maximum operating frequency of 1.9GHz at 1.1V.
Date of Conference: 11-16 June 2023
Date Added to IEEE Xplore: 24 July 2023
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