Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.

I. Proposed Vision

Today's tremendous interdisciplinary efforts towards building a quantum computer is aimed at a machine capable of tackling problems beyond the reach of any classical computer. The so-called quantum advantage, a term referring to a quantum computer performing a specific computation that is intractable for a classical computer, has been recently claimed with state-of-the-art Noisy Intermediate-Scale Quantum (NISQ) computers consisting of several tens of quantum bits (qubits) [1]. Nevertheless, it is widely recognized that addressing any real-world problem will require upscaling to thousands or even millions of qubits [2]. Scaling quantum computers to such a large number of qubits is a major challenge due to, among others, the confluence of (i) technology factors confining the qubits to low fidelity, (ii) the need for cryogenic temperatures to reach practical coherence times, (iii) the dense integration of digital/RF control circuits, which are needed on a per-qubit basis [3], and (iv) the manifold architectural and algorithmic implications of managing noisy and short-lived qubits. The scaling-up race is fiercely complex and mostly revolves around the qubit technological aspects, but the bottleneck will very soon shift to the architectural problems stemming from the need to densely pack together the qubits and their classical electronics interfaces. Fig. 1:

The multi-qcore architectural vision.