A Neural-Recording 0.2-V VCO-based ADC with Machine-Learning-Programmable Coupled Oscillator Ensembles

Future energy-harvesting (EH) brain-machine interfaces (BMI) present fundamental design challenges to analog-to-digital converters (ADC) for neural signal digitisation and recording. Ultra-low power (ULP) consumption, maximised area density, bandwidth and dynamic range as well as amenability to ultra-low voltage (ULV) supply are all desirable performance specifications. This article presents a digitally intensive openloop voltage-controlled-oscillator (VCO)-based ADC operating at an ULV supply of only 0.2V in 28nm CMOS. We introduce a novel design framework harnessing the spatio-temporal dynamics of coupled oscillator ensembles (COE) for open-loop voltage-to-frequency (V -to-f) analog linearisation, as applied to high impedance input transconductor-driven VCOs. A machine learning (ML)-driven foreground calibration engine employing gradient descent automatically optimises the integrated digitally programmable ‘tuning knobs’ of the COE network to guide its self-adaptive linearisation. A Verilog-A calibration engine integrated with the transistor level COE was developed to perform full-system transient simulations (lasting several miliseconds) which reduced the dominant third-order harmonic distortion (HD3) from −35dBc to −70dBc for a near rail-to-rail differential input voltage swing of ±180mV, verifying the calibration process.