15 nA CMOS Analog Voltage Buffer Insensitive to PVT Variations | IEEE Conference Publication | IEEE Xplore

15 nA CMOS Analog Voltage Buffer Insensitive to PVT Variations


Abstract:

An ultra-low current CMOS analog voltage buffer for use in conjunction with a voltage reference circuit is described. Despite the fairly standard topology, this study dem...Show More

Abstract:

An ultra-low current CMOS analog voltage buffer for use in conjunction with a voltage reference circuit is described. Despite the fairly standard topology, this study demonstrates that subthreshold operation with proper transistor sizing provides buffer performance that accurately matches that of the reference voltage circuit driving the buffer. In this way, there is no appreciable deterioration in terms of insensitivity to process, temperature, and supply voltage variations for the entire buffered reference voltage. The buffer consumes 15 nA of standby current and is able to drive a 20-pF load with a nominal open-loop gain greater than 100 dB, ensuring a closed-loop accuracy better than 0.01%. The buffer works properly under a supply voltage ranging from 1.2 V to 5 V. Moreover, under a 3-V supply, the mean value of the buffered voltage is 405.65 mV with a standard deviation of 7.44 mV in the temperature range of −40°C to 125°C.
Date of Conference: 18-21 June 2023
Date Added to IEEE Xplore: 29 June 2023
ISBN Information:
Conference Location: Valencia, Spain

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