An Open-Source Static Timing Analysis EDA Tool for Digital System Design

Static timing analysis (STA) is an EDA tool used for Digital System Design to compute the expected delay/timing of a synchronous digital circuit without requiring a simulation of the full circuit. High-performance VLSI designs have traditionally been characterized by the clock frequency at which they operate. Estimation of a circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous abstraction levels. Moreover, delay calculation must be incorporated into the inner loop of timing optimizations at various steps of design, such as logic synthesis, layout design, PNR (placement and routing), and in in-place optimizations performed late in the design cycle. There are high-end Industrial EDA tools available, but this paper addresses the need of a low-cost solution for STA. The paper proposes a novel aspect of an open-source EDA tool to find the critical path of Digital Design. The tool is developed using Python Language. The netlist format used for this tool is a modified version of gate level ISCAS netlist format which included the information on circuit structure and the gate and net delays can be provided by the user. The developed tool provides a visual impression of the design in the form of a directed acyclic graph (DAG) and highlights the critical path. The tool aims to provide assistance in digital designing for STA and help the designer provide modification in case of a timing violation (Setup or Hold).