A Digital Delay Model Supporting Large Adversarial Delay Variations

Dynamic digital timing analysis is a promising alternative to analog simulations for verifying particularly timing-critical parts of a circuit. A necessary prerequisite is a digital delay model, which allows to accurately predict the input-to-output delay of a given transition in the input signal(s) of a gate. Since all existing digital delay models for dynamic digital timing analysis are deterministic, however, they cannot cover delay fluctuations caused by PVT variations, aging and analog signal noise. The only exception known to us is the η-IDM introduced by Függer et al. at DATE’18, which allows to add (very) small adversarially chosen delay variations to the deterministic involution delay model, without endangering its faithfulness. In this paper, we show that it is possible to extend the range of allowed delay variations so significantly that realistic PVT variations and aging are covered by the resulting extended η-IDM.

I. Introduction

Accurate signal propagation predictions are crucial for modern digital circuit design. The highest accuracy is currently achievable by analog simulations, e.g., using SPICE. These suffer, however, from excessive running times. A considerably more efficient alternative is dynamic digital timing analysis, which traces individual signal transitions throughout a circuit. Application examples are clock trees or time-based encoded inter-neuron links in hardware-implemented spiking neural networks [1], where the (very accurate but worst-case) delay estimates provided by classic static timing analysis techniques like CCSM [2] and ECSM [3] are not sufficient for ensuring correct operation.