TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction

Floorplanning, as an early step in physical design, will greatly affect the PPA of the later stages. To achieve better performance while main-taining relatively the same chip size, the utilization of the generated floorplan needs to be high and constraints related to design rules, routability, power should be honored. In this paper, we propose a two-step framework, called TOFU, for floorplan whitespace reduction with fixed-outline and soft/pre- placed/hard modules modeled. Whitespace is first reduced by iteratively refining the locations of modules. Then the modules near whitespace will be changed into rectilinear shapes to further improve the utilization. To ensure the legality and quality of the intermediate floorplan during the refinement process, a constraint graph-based legalizer with a novel constraint graph construction method is proposed. Experimental results show that the whitespace of the initial floorplans generated by Corblivar [1] can be reduced by about 70% on average and up to 90% in several cases. Moreover, the resulting wirelength is also 3% shorter due to a higher utilization.

I. Introduction

Floorplanning has been one of the most crucial stages in modern physi-cal design flow. Having the same chip size, a decent floorplan with higher utilization and shorter wirelength will normally lead to a more compact design with better power, performance, and area (PPA). In alignment with the emerging real-world physical implementation requirements, more constraints have been added to the classical floorplanning problem. As mentioned in [2], floorplanning with a predetermined outline is more practical as it enables hierarchical design for the increasingly complex circuits. Besides, a modern floorplanning algorithm should consider pre-placed modules (PPM).