Design and Implementation of Power Efficient 8:1 Multiplexer using PTL Technology

The development in the methodologies of fundamental functional units of digital systems have raised the attention due to advancement in CMOS technology. Continuous demand of battery-powered portable electronics like cell phones, PDAs, and notebook computers has forced us to ensure low power dissipation in the CMOS circuits. One of the fundamental building blocks in digital design, MUX has been a major area of research interest for many years. System designers are showing a great emphasis on functional unit energy efficiency and technology scaling as a result. Ensuring low power consumption and building low power systems is a great challenge in the design of VLSI chips today and has become one of the key aspects of the electronic industries. In this article, fredkin gate is created using traditional PTL for developing an S:1 MUX. The circuit’s power consumption is decreased as it is having fewer transistors. Initially in conventional 8:1 MUX the number of transistors used was more than 42. [1] In our article we have fredkin gate and hence the number of transistors can be reduced to 42. Hence a drop considerable drop in power consumption of 5-15 percent is observed.