Analysis of 6T Full Adder using 2T XOR and 2T XNOR Module

Power consumption and delay factors are the main design restrictions in the developing nanometer technology Schematics. The major component of an ALU, or Arithmetic logic unit, of a processor is the full adder. Therefore, altering the Full Adder’s parameters in a significant way will directly affect the ALU’s and then the Processor’s parameters. This paper proposes designing a 6T full adder using 2T XOR and 2T XNOR modules using Cadence Virtuoso GPDK 90nm technology. The 2T XOR and 2T XNOR modules will then be replaced with CPTL logic in the 6T full adder. The 2T XOR module using PTL has the lowest PDP of 109.38 and the 2T XOR module using CPTL has the lowest delay of 7. 17Sps. The conclusion drawn from the parametric analysis of output noise, power consumption, and delay obtained from the proposed circuits will then be presented in this paper.

I. Introduction

Full Adder adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-in. The output carry will be C-out, and the standard output will be S, which stands for Sum. Circuit design for low area has become a serious challenge as integrated circuits have progressed toward extremely high integration density and high operating frequencies.