Analysis of Vmin Variability in Complex Digital Logic via Post-Silicon Profiling

Energy efficiency of electronic devices has risen to become the top concern in recent years. Lowering minimum operating voltage (Vmin) without sacrificing performance is a direct way to reduce power consumption and improve energy efficiency. However, Vmin is affected by a complex interaction of factors including design systematics, process variation, manufacturing excursions, workloads, and operating environment. This paper presents a method to obtain post-silicon profiles from scan-based design-for-test (DFT) structures already found in practically all modern digital designs. Data analysis of the fine-grain profiles allows us to localize areas of high voltage margin sensitivity and tease apart design versus manufacturing factors. With a better understanding of such factors, we can develop strategies to reduce a design's overall Vmin as well as improve its manufacturing bin yields.