A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage

Pipelined SAR ADCs have become popular due to their excellent speed, resolution, and power efficiency. In advanced processes, the single-channel pipelined SAR ADC has gone beyond 1GS/s with $\geq$10b resolution [1–2]. The key operation in a pipelined SAR is the residue amplification (RA) which realizes residue transfer and provides interstage gain, but it also constitutes the speed bottleneck. Fig.1 (top) depicts the typical time allocation of the three-stage pipelined SAR architecture that is widely adopted to achieve both high resolution and speed. The current and next stages both need to participate in the current-stage residue amplification, consuming a significant timing budget for each stage. A high-bandwidth residue amplifier can reduce its amplification time, but it is power-hungry especially for the critical lst-stage residue amplifier that requires both high linearity and gain. Removing the time-consuming residue amplification and using passive residue transfer can tackle this bottleneck [3]. However, the lack of interstage gain increases the noise and linearity requirement for the succeeding stages, thereby limiting the ADC accuracy. In this work, we present a new pipelined RA stage scheme that allows the RA to run in parallel with the SAR conversions, thus breaking the speed bottleneck. To achieve both high bandwidth and power efficiency, we use a fast fully differential ring amplifier and a high-speed open-loop amplifier to implement the critical $1^{\mathrm{s}\mathrm{t}}-$stage and relaxed $2^{\mathrm{n}\mathrm{d}}-$stage RAs, respectively. The 12b single-channel prototype operates at 1. 5GS/s and achieves 58. 5dB SNDR with a Nyquist input while consuming 21.3mW.