A Comprehensive Analysis of the Architecture of Static Random Access Memory Utilizing CMOS for Mobile Applications

The modern electronic industry is always searching for ways to improve its power efficiency and processing speed. Because of this, SRAM is included in every IC to increase its functionality. The utilization of high-tech devices that rely on memory like RAM is the outcome of the technology's rapid advancement for matter and speedier invention to smooth out human necessities like mobile. The size and power consumption to fulfill the growing demand is the goal. To optimize latency and power, this research study focuses on a comprehensive investigation of SRAM (static random access memory). In this study, the performance of read and write operations for SRAM cells supporting a 6T, 9T, and 10T configuration is compared. In this study, a new SRAM is developed to meet the needs of low-power, high-performance circuits. Major chip space is used by the SRAM block, which causes leakage of power in more contemporary systems. Scaling the voltage supply of SRAM macros is an effective way to lower chip power overall. Conventional 6T SRAMs cannot meet the demands for density and yield in the sub-threshold area. Reducing the power and area of SRAM is the aim of this work. We compare the new (4T) SRAM and 32 nm CMOS technique with the conventional six-transistor (6T) RAM cell. Here, many SRAM cell configurations for one-bit, sixteen-bit, sixty-four-bit, and one Kb may be developed and tested, employing both a unique load-less 4T SRAM unit & 6T SRAM unit using 32nm CMOS technology. The novel load-less 4T SRAM array takes less energy so it occupies a smaller region than a 6T array.