VLSI Implementation of Blanking Cover Pulse and CBCP module Propagation for External System Interface

External system is a subsystem which is a part of a receiver application. The Composite Blanking Cover Pulse module (CBCP) is one of the major functional modules which need to be designed & developed for the External Sub-system. The external system (target hardware) is designed and developed based on Virtex 5 FPGA. The function of Composite Blanking Cover Pulse Module is that it will receive Input Trigger Pulse from various subsystems in different frequency bands on pulse-pulse basis and in turn generates respective blanking cover pulses for all the input trigger pulses. Subsequently, using these individual blanking cover pulses, a final composite cover pulse using various time parameters need to be generated on a pulse-topulse basis. The composite blanking cover pulse module uses various pulse parameters and various timing parameters for generation of composite blanking cover pulse. This CBCP is very essential to safeguard the main ESM system. The Master clock is used in 40 MHz All the intermediate control/signals should be synchronous with respect to master clock. The entire firmware must be developed using VHDL language. Finally, all the developed code is tested for its complete functionality in the simulated environment using Xilinx ISE (14.7) software [6].