Abstract:
Analog circuit sizing is a high-cost process in terms of the man-ual effort invested and the computation time spent. With rapidly developing technology and high market de...Show MoreMetadata
Abstract:
Analog circuit sizing is a high-cost process in terms of the man-ual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing auto-mated solutions for sizing has attracted great attention. This pa-per presents APOSTLE, an asynchronously parallel optimization method for sizing analog transistors using Deep Neural Network (DNN) learning. This work introduces several methods to minimize real-time of optimization when the sizing task consists of several different simulations with varying time costs. The key contributions of this paper are: (1) a batch optimization framework, (2) a novel deep neural network architecture for exploring design points when the existed solutions are not always fully evaluated, (3) a ranking approximation method based on cheap evaluations and (4) a theo-retical approach to balance between the cheap and the expensive simulations to maximize the optimization efficiency. Our method shows high real-time efficiency compared to other black-box op-timization methods both on small building blocks and on large industrial circuits while reaching similar or better performance.
Date of Conference: 16-19 January 2023
Date Added to IEEE Xplore: 23 February 2023
Electronic ISBN:978-1-4503-9783-4
ISSN Information:
Conference Location: Tokyo, Japan