1 Introduction
Various and serious hardware threats are emerging throughout the lifecycle of integrated circuits (ICs). Many seminal threats are ex-ecuted post-design stage, which we can not ensure security once the physical design is done. For example, there is no way to ensure that the layout has not been inserted by hardware Trojan and other unknown threats after the manufacturing is completed [12]. Simi-larly, we can not prevent probing attacks that can access, monitor, and extract sensitive information at the running time of a chip [9]. However, electronic design automation (EDA) tools traditionally optimize PPA, and there is currently little to no experience related to designing secure ICs available within the EDA community [4].