WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code

Large error rates of quantum bits (qubits) are one of the main difficulties in the development of quantum computing. Performing quantum error correction (QEC) with surface codes is considered the most promising approach to reduce the error rates of qubits effectively. To perform error correction, we need an error-decoding unit, which estimates errors in the noisy physical qubits repetitively, to create a robust logical qubit. While complicated graph-matching problems must be solved within a strict time restriction for the error decoding, several hardware implementations that satisfy the restriction at a large code distance have been proposed. However, the existing decoder designs are still challenging in reducing the logical error rate. This is because they assume that the error rates of physical qubits are uniform while they have large variations in practice. According to our numerical simulation based on the quantum chip with the largest qubit number, neglecting the non-uniform error properties of a real quantum chip in the decoding process induces significant degradation of the logical error rate and spoils the benefit of QEC. To take the non-uniformity into account, decoders need to solve matching problems on a weighted graph, but they are difficult to solve using the existing designs without exceeding the time limit of decoding. Therefore, a decoder that can treat both the non-uniform physical error rates and the large surface code is strongly demanded. In this paper, we propose a hardware design of decoding units for the surface code that can treat the non-identical error properties with small latency at a large code distance. The key idea of our design is 1) constructing a look-up table for calculating the shortest paths between nodes in a weighted graph and 2) enabling parallel processing during decoding. The implementation results in field programmable gate array (FPGA) indicate that our design scales up to code distance 11 within a microsecond-level delay, which is comparable to the existing state-of-the-art designs, while our design can treat non-identical errors.

1 Introduction

Quantum computing is an emerging computing paradigm for potential practical use since it enables us to use properties of quantum matters, such as superpositions and entanglements, for faster pro-cessing in several applications [1], [8], [1] [8]. On the other hand, since the lifetime of computational elements, called a quantum bit (qubit), is limited up to hundreds of microseconds [2] due to heating and calibration noise [12], the reliability of current quantum devices is not enough for their practical applications [13]. To cope with this problem, we can construct a logical qubit with noisy physical qubits using quantum error-correcting (QEC) codes. By checking the error parities with a sufficiently faster period than the lifetime of qubits repetitively and by increasing the code distance, i.e., using more physical qubits in the code, the occurred errors can be reliably estimated and corrected, and error rates of logical qubits can be suppressed to an arbitrarily small value [7], [17]. This error-estimation task is called a decoding process. Currently, surface codes [6] are believed to be the most promising QEC codes, since they can be implemented with nearest-neighboring interactions on two-dimensional grids and show high error-correction performance. While the surface codes still require decoders to solve complicated graph-matching problems within a strict time restriction, several hardware implementations that satisfy the restriction at a large code distance have been proposed.