Hardware Trojan Detection and High-Precision Localization in NoC-based MPSoC using Machine learning | IEEE Conference Publication | IEEE Xplore

Hardware Trojan Detection and High-Precision Localization in NoC-based MPSoC using Machine learning


Abstract:

Networks-on-Chips (NoC) based Multi-Processor System-on-Chip (MPSoC) are increasingly employed in industrial and consumer elec-tronics. Outsourcing third-party IPs (3PIPs...Show More

Abstract:

Networks-on-Chips (NoC) based Multi-Processor System-on-Chip (MPSoC) are increasingly employed in industrial and consumer elec-tronics. Outsourcing third-party IPs (3PIPs) and tools in NoC-based MPSoC is a prevalent development way in most fabless companies. However, Hardware Trojan (HT) injected during its design stage can maliciously tamper with the functionality of this communication scheme, which undermines the security of the system and may cause a failure. Detecting and localizing HT with high pre-cision is a challenge for current techniques. This work proposes for the first time a novel approach that allows detection and high-precision localization of HT, which is based on the use of packet information and machine learning algorithms. It is equipped with a novel Dynamic Confidence Interval (DCI) algorithm to detect ma-licious packets, and a novel Dynamic Security Credit Table (DSCT) algorithm to localize HT. We evaluated the proposed framework on the mesh NoC running real workloads. The average detection precision of 96.3% and the average localization precision of 100% were obtained from the experiment results, and the minimum HT localization time is around 5.8 ~ 12.9us at 2GHz depending on the different HT-infected nodes and workloads.
Date of Conference: 16-19 January 2023
Date Added to IEEE Xplore: 23 February 2023
Electronic ISBN:978-1-4503-9783-4

ISSN Information:

Conference Location: Tokyo, Japan

1 Introduction

The significant rise in the outsourcing level in the hardware supply chain has led to the emergence of new security threats at the circuit level, for instance, Hardware Trojan (HT). The latter is a malicious modification of circuit or architecture in the hardware, especially in chip-level devices. Network on Chip (NoC) is an architecture that has been commonly used to inject an HT. Three of the total five security issues in NoC-based SoCs summarised in [5] can be induced by HT, which makes a non-negligible threat for NoC. In the modern Integrated Circuit (IC) supply chain, HT injection can be implemented during RTL design, Netlist/Gate Level Design, and Physical Design, because untrustworthy Third-party Intellectual Property (3PIP) cores and third-party Electronic Design Automation (3PEDA) tools are commonly introduced in these three stages [17]. The commercial NoC-based SoC generally outsources up to hundreds of different 3PIPs from all around the world and expe-riences longer periods of development using 3PEDA tools, which compels engineers pay more attention to its security as it has a higher possibility of HT injection. Furthermore, detecting and even localizing HT during design time using static IP /SoC verification is difficult [10], for this reason, methods of runtime HT detection and localization have been emerging. Additionally, the utilization of machine learning (ML) in NoC security is increasing as ML is effective in anomalous classification and detection, especially in the complicated heterogeneous multi-core system. HTs can destroy the system or steal confidential information by maliciously tampering with transmission information, which is one of the Denial-of-Service (DoS) attacks. The HT-injected router, Network Interface (NI), and outsourced IP core [4] of the NoC are the main hiding places of HT, where the packets can be maliciously tampered with to interpose traffics. HT can be detected by directly monitoring its attacks, and several works related to it have been done: [9] trained and deployed an SVM algorithm to detect DoS at-tacks in a customized NoC for biomedical applications; DoS attacks can also be detected by employing Gradient Boosting classifier in [13]; a novel router architecture embedded with a DetectANN mod-ule for HT detection and bypass malicious data to mitigate the HT effectiveness was proposed in [14]. Apart from HT detection, HT localization has the more significance: [3] utilized timing violation of packets to detect and localize HT in NoC, which achieved the lo-calization time of 8~ 24us; Yao in [18] proposed a framework with both detection and localization of DoS in NoC, but it has a drawback of directly regarding the source node as HT injected but ignoring all nodes in the routing path of packets. This work proposed an ML-based fast HT detection and high-precision localization frame-work, which covers the gap between using ML to detect tampering attacks on typical mesh NoC architecture and precisely localizing HT in a short time, enhancing the speed to mitigate HT in advance. The threat model in this work is malicious tampering which is a packet corruption attack and leads to a consequence of DoS [5]. The main contributions are listed as follows.

We proposed an HT detection and high-precision localization framework for NoC. The framework combined ML with packets' attributes to precisely localize HT for the first time.

We designed the experiment for validating the effectiveness of the proposed framework. An HT injection module was designed to simulate the behavior of the real HT circuit in a malicious node and to generate HT-infected datasets.

We tested and analyzed the complete security framework. The representative performance evaluation metrics were employed. A comparison between the state-of-the-art HT detection & localization approaches with our work was achieved.

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